FIG. 5 shows an integrated semiconductor memory 100′, which is formed, for example, as a DRAM (Dynamic Random Access Memory) semiconductor memory. The integrated semiconductor memory comprises a memory cell array 10 in which memory cells are arranged in matrix form along word lines and bit lines. In the example of FIG. 5, the memory cell array comprises a word line WL, to which memory cells SZ1, SZ2, and SZ3 are connected. The cells formed as DRAM memory cells comprise a selection transistor AT and a storage capacitor SC. One capacitor plate of the storage capacitor is connected to a true bit line BTt via the selection transistor AT. The other capacitor plate is connected to a terminal for application of a plate voltage Vplate. The plate voltage Vplate may be formed as a ground potential, by way of example.
A complement bit line BCt exists besides the true bit line BTt. The true bit line BTt and complement bit line BCt represent a bit line pair which is connected to a sense amplifier SA1 on a right-hand side of the memory cell array. During the read-out of the memory cell SZ1, the sense amplifier SA1 generates at an output terminal A1, in accordance with the memory state stored in the memory cell SZ1, a datum D, which is fed to a data terminal DQ.
Besides the sense amplifier SA1, a further sense amplifier SA3 exists on the right-hand side of the memory cell array. The sense amplifier SA3 is connected to a bit line pair that comprises a true bit line BTb and a complement bit line BCb. A memory cell SZ3 is connected to the true bit line BTb, and is likewise connected to the word line WL for activation. During the read-out of the memory cell SZ3, in accordance with the memory state of the memory cell SZ3, the sense amplifier SA3 generates at its output terminal A3 a datum which is fed to the data terminal DQ.
Arranged between the upper bit line pair BTt/BCt and the lower bit line pair BTb/BCb is a further bit line pair. This bit line pair comprises a true bit line BTm and a complement bit line BCm. Both bit lines are connected to a further sense amplifier SA2 arranged on the left-hand side of the memory cell array 10. A memory cell SZ2 is connected to the true bit line BTm and is likewise connected to the common word line WL for activation. During the read-out of the memory cell SZ2, the sense amplifier SA2 generates at an output terminal A2, in accordance with the memory state of the memory cell SZ2, a datum, which is fed to the data terminal DQ.
In addition to the word line WL, a further word line WLr is arranged within the memory cell array 10, the further word line being formed as a redundant word line with respect to the word line WL. A memory cell SZ1r is connected to the redundant word line WLr and its memory state is evaluated by the sense amplifier SA1 during read-out. Furthermore, a redundant memory cell SZ2r is connected to the redundant word line WLr and its memory state is evaluated by the sense amplifier SA2. A memory state of a further redundant memory cell SZ3r, which is likewise connected to the redundant word line WLr, is evaluated by the sense amplifier SA3.
In addition to the sense amplifiers SA1 and SA3, further sense amplifiers with their associated bit line pairs are arranged on the right-hand side of the memory cell array. Situated between the bit line pairs which are connected to sense amplifiers on the right-hand side of the memory cell array are further bit line pairs connected to further sense amplifiers on the left-hand side of the memory cell array in an alternating manner.
Prior to a read access, all the bit lines of the memory cell array 10 are charged to a common precharge voltage VEQ. The precharge voltage VEQ lies between a high voltage potential VBH and a low voltage potential VBL.
A read access to the memory cell SZ1 is described below with reference to FIGS. 5 and 6. For the read-out of the memory cell SZ1, an address of the memory cell SZ1 is applied to an address terminal A30 and is read into an address register 30. The actual read access to the memory cell SZ1 is controlled by a control circuit 20. For this purpose, the control circuit 20 is driven by a command signal KS at a control terminal S20. In response to the read command KS, the control circuit 20 drives the word line WL for activating the memory cell SZ1 with a high level of a word line voltage VWH. The selection transistor AT of the memory cell SZ1 is thereby controlled into the on state, so that the storage capacitor of the memory cell SZ1 is conductively connected to the bit line BTt. Since all the remaining memory cells along the word line WL are also driven by the high level of the word line voltage, the memory cells SZ2 and SZ3 are also activated by virtue of the selection transistors AT of the memory cells likewise being controlled into the on state.
FIG. 6 shows potential states on the bit lines BTt and BCt for reading out a “1” information item from the memory cell SZ1. Due to the high charge level corresponding to the “1” information item on the storage capacitor SC, a potential increase occurs on the true bit line BTt relative to the precharge voltage VEQ to which the complement bit line BCt is charged. After a so-called signal development time, the sense amplifiers SA1 and SA3 on the right-hand side of the memory cell array and the sense amplifier SA2 on the left-hand side of the memory cell array are driven simultaneously by an activation signal ACT. The sense amplifiers thereupon evaluate the slight potential difference on the true bit line connected to them and the complement bit line connected to them. In the example of FIG. 6, the sense amplifier SA1 amplifiers the potential increase on the true bit line BTt to the high voltage level VBH and the voltage level of the precharge voltage VEQ on the complement bit line BCt to the low voltage level VBL.
In order to ensure the described proper operating behavior of an integrated semiconductor memory, the memories are subjected to comprehensive functional tests during and after fabrication. If a defective component is discovered within the memory cell array, an attempt is made to replace the defective component with a redundant component. Arranged in the memory cell array 10 is a redundant word line WLr, for example, to which redundant memory cells SZ1r, SZ2r, and SZ3r are connected. When a memory fault occurs in one of the regular memory cells SZ1, SZ2, or SZ3, instead of the faulty regular memory cell, one of the redundant memory cells is used for the read and write access to it by virtue of the redundant word line WLr being driven instead of the word line WL.
In order to cover as many fault causes as possible, different fault-specific data topologies are stored in the memory cells of the memory cell array. The memory states stored the memory cells are subsequently influenced by stress voltages. Thus, during a test, by way of example, the word line voltage on an adjacent word line is changed, the precharge voltage VEQ is varied or the plate voltage Vplate is changed. In order to cover as many fault causes as possible, many different data topologies have to be stored in the memory cell array, which leads to a long test time.